82870P2P64H2 Datasheet, PDF (27/217 Pages) –

Signal Description
R
2.3
PCI Bus Interface Clocks and Reset
There are two sets of PCI Bus clock and reset signals: one for PCI Bus A and one for PCI Bus B.
Table 6. PCI Bus Interface Clocks and Reset Interface A Signals
Signal
PAPCLKO[6:0]
PAPCLKI
PAPCIRST#
BPCLK100
BPCLK133
Type
Description
PCI Clock Output: These signals provide 33/66/100/133 MHz clock for a PCI
O device. PAPCLKO6 is connected to the PAPCLKI input. It must be externally
connected.
PCI Clock In: This signal is connected to an output of the low skew PCI clock
I buffer tree. It is used by the PLL to synchronize the PCI clock driven from
PCLKOUT to the clock used for the internal PCI logic.
PCI Reset: The Intel® P64H2 asserts PCIRST# to reset devices that reside on
the secondary PCI bus. The P64H2 asserts PCIRST# due to one of the
following events:
O
• RSTIN#
• Setting the PCI Reset (bit 6) in the Bridge Control Register.
Bypass Clock – 100 MHz: This clock input can be up to 100 MHz, and will be
I driven by the P64H2 as the PCI-X clock if in bypass mode and the PCI-X
frequency is supposed to be 100 MHz.
Bypass Clock – 133 MHz: This clock input can be up to 133 MHz, and will be
I driven by the P64H2 as the PCI-X clock if in bypass mode and the PCI-X
frequency is supposed to be 133 MHz.
Intel^® 82870P2 P64H2 Datasheet
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