82870P2P64H2 Datasheet, PDF (132/217 Pages) –

Functional Description
R
4.2.15.2
Behavior of Hub Interface Initiated Cycles to PCI-X Receiving Split
Terminations
The behavior described in the following table is independent of the Master Abort Mode bit and
whether or not the cycle is exclusive (locked) or not. P64H2 will return all 1s on all data bytes for
a read completion that terminates in either Master Abort or Target Abort on the hub interface.
Note that when a target or master abort is returned on the hub interface, the attached PCI/PCI-X
bus is not locked. This is of special importance to the completion messages of data parity error,
byte count out of range, write data parity error, device specific, and reserved / illegal codes.
P64H2 must not lock its bus on these errors, even though they are not explicitly master or target
aborts on the PCI-X interface.
Table 34. Split Terminations of Completion Required Cycles to PCI-X
PCI-X Split
Termination
Message
Class Index
Hub Interface
Completion
Status Register Bits Sets
Successful
Master Abort
Target Abort
0
00h
1
00h
1
01h
Write Data Parity Error
1
02h
Byte Count Out of Range
2
00h
Write Data Parity Error
2
01h
Device Specific
Reserved/Illegal
2
8Xh
Others
Successful
Master Abort
Target Abort
Target Abort
Target Abort
Target Abort
Target Abort
Target Abort
• Master Data Parity Error (Sec), if
encountered
• Received Master Abort (Sec)
• Received Target Abort (Sec)
• Signaled Target Abort (Pri)
• Master Data Parity Error (Sec)
• Signaled Target Abort (Pri)
• Signaled Target Abort (Pri)
• Master Data Parity Error (Sec)
• Signaled Target Abort (Pri)
• Signaled Target Abort (Pri)
• Signaled Target Abort (Pri)
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Intel^® 82870P2 P64H2 Datasheet