82870P2P64H2 Datasheet, PDF (134/217 Pages) –

Functional Description
R
4.2.16
is detected on the hub interface, the P64H2 will stop the current sequence for that data (if it was
running) and generate the Split Completion Error Message.
Configuration Transactions
Type 0 configuration transactions are issued when the intended target resides on the same PCI-X
bus as the initiator. A Type 0 configuration transaction is identified by the configuration command
and the lowest 2 bits of the address set to 00b.
Type 1-configuration transactions are issued when the intended target resides on another PCI-X
bus, or when a special cycle is to be generated on another PCI-X bus. A Type 1 configuration
command is identified by the configuration command and the lowest 2 address bits set to 01b.
The register number is found in both Type 0 and Type 1 formats and gives the DWord address of
the configuration register to be accessed. The function number is also included in both Type 0 and
Type 1 formats and indicates which function of a multifunction device is to be accessed. For
single-function devices, this value is not decoded. Type 1 configuration transaction addresses also
include a 5-bit field designating the device number that identifies the device on the target PCI-X
bus that is to be accessed. In addition, the bus number in Type 1 transactions specifies the PCI-X
bus to which the transaction is targeted.
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Intel^® 82870P2 P64H2 Datasheet