82870P2P64H2 Datasheet, PDF (53/217 Pages) –

Register Description
R
3.2.25
PX_CAPID—PCI-X Capabilities Identifier Register
(D29,31: F0)
Offset:
50h
Default Value: 07h
Attribute:
Size:
RO
8 bits
This register identifies this item in the Capabilities list as a PCI-X register set. It returns 07h when
read.
Bits
Description
7:0 Identifier (ID). This field has a value of 07h that indicates this is a PCI-X capabilities list.
3.2.26
PX_SSTS—PCI-X Secondary Status Register (D29,31: F0)
Offset:
52–53h
Default Value: 0003h
Attribute:
Size:
R/WC, RO
16 bits
This is the PCI-X command register, which controls various modes of the bridge.
Bits
Description
15:9 Reserved
Secondary Clock Frequency (SCF)—RO. This field is set with the frequency of the secondary
bus.
Bits
Max Frequency Clock Period
000
PCI Mode
N/A
8:6
001
66 MHz
15
010
100 MHz
10
011
133 MHz
7.5
1xx
Reserved
Reserved
Split Request Delayed. (SRD)—RO. Hardwired to 0. This bit is intended to be set by a bridge if
5
it cannot forward a transaction on the secondary bus to the primary bus because there is not
enough room within the limit specified in the Split Transaction Commitment Limit field in the
Downstream Split Transaction Control Register. The Intel® P64H2 never sets this bit.
Split Completion Overrun (SCO)—RO. Hardwired to 0. This bit is intended to be set if a bridge
4
terminates a Split Completion on the secondary bus with retry or Disconnect at the next ADB
because its buffers are full. The P64H2 never sets this bit.
Unexpected Split Completion (USC)—R/WC.
0 = No unexpected split completion received.
3
1 = This bit is set if an unexpected split completion with a requester ID equal to the P64H2’s
secondary bus number, device number 00h, and function number 0 is received on the
secondary interface.
Note: Software clears this bit by writing a 1 to it.
Intel^® 82870P2 P64H2 Datasheet
53