82870P2P64H2 Datasheet, PDF (122/217 Pages) –

Functional Description
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4.1.9.6
4.1.9.7
4.1.9.8
4.1.9.9
Write Transactions on Hub Interface (Intel^® P64H2 As Hub Interface
Target)
When the P64H2 detects a data parity or multi-bit ECC error on a hub interface write request, it:
• Sets the Data Parity Error Detected bit (bit 15) in the PD_STS Register
(offset 06–07h) of the target interface (APIC, hot plug, PCI bridge primary).
• If decoded by the bridge, it forwards the bad parity with the data to PCI. If the cycle is
decoded by the APIC or the hot plug controller, (memory writes only), does not perform the
write.
• Initiates the DO_SERR special cycle and sets the Signaled System Error bit (bit 14) in the
PD_STS Register, if the Parity Error Response bit (bit 6) is set in the PD_CMD Register.
If a single bit ECC error is detected, it is corrected and none of the above occurs.
Write Transactions on Hub Interface (Intel^® P64H2 As Hub Interface
Master)
There is no way of detecting that the MCH detected a parity error from a hub interface posted
write from PCI. Therefore, no action is taken by the P64H2.
Write Transactions on PCI (Intel^® P64H2 As PCI Target)
When the P64H2 detects a data parity error on a PCI write, it:
• Asserts PERR# two cycles after the data transfer, if the secondary interface parity error
response bit is set in the Bridge Control Register.
• Sets the secondary interface Parity Error Detected bit in the Secondary Status Register.
• Forces bad parity or a multi-bit ECC error condition to the primary bus.
Write Transactions on PCI (Intel^® P64H2 As PCI Master)
When a data parity error is reported on the PCI bus from a hub interface or PCI peer initiated write
request by the target’s assertion of PERR#, the P64H2:
• Sets the Detected Parity Detected bit (bit 8) in the Secondary Status Register (offset 1E–1Fh),
if the secondary interface parity error response bit is set in the bridge control register.
• Initiates DO_SERR special cycle and sets the Signaled System Error bit in the PD_STS
Register, if all of the following conditions are met:
• The SERR# enable bit is set in the PD_CMD Register.
• The Secondary Interface Parity Error Response bit is set in the Bridge Control Register.
• The Primary Interface Parity Error Response bit is set in the PD_CMD Register.
• The P64H2 did not detect the parity error on the hub interface (i.e., the parity error was not
forwarded from the hub interface).
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Intel^® 82870P2 P64H2 Datasheet