82870P2P64H2 Datasheet, PDF (52/217 Pages) –

Register Description
R
Bits
Description
Delayed Transaction Depth (DTD)—R/W. This bit controls the number and size of P64H2’s
delayed transaction butters. This bit should be left at its default of 0b.
2
0 = 4 Delayed Transaction Buffers (each 1024 bytes) when 33/66 MHz;
2 Delayed Transaction Buffers (each 2048 bytes) when 100/133 MHz
1 = 4 Delayed Transaction Buffers, each at 1024 bytes at all frequencies
Maximum Delayed Transactions (MDT)—R/W. This field controls the maximum number of
delayed transactions the P64H2 is allowed to have.
1:0
00 = 4 active, 4 pending
01 = 1 active, 1 pending
10 = 2 active, 2 pending
11 = Reserved
3.2.23
MTT—Multi-Transaction Timer Register (D29,31: F0)
Offset:
42h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register controls the amount of time that the P64H2’s arbiter allows a PCI initiator to perform
multiple back-to-back transactions on the PCI bus. The number of clocks programmed in the
Multi-Transition Timer represents the guaranteed time slice (measured in PCI clocks) allotted to
the current agent, after which the arbiter will grant another agent that is requesting the bus.
Bits
Description
Timer Count Value (MTC). This field specifies the amount of time that grant remains asserted to
7:3 a master continuously asserting its request for multiple transfers. This field specifies the count in
an 8-clock (PCI clock) granularity.
2:0 Reserved
3.2.24
STRP—PCI Strap Status Register (D29,31: F0)
Offset:
44h–47h
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
This register indicates the states of various straps for this PCI interface.
Bit
Description
31:2 Reserved
HPCAP. This bit indicates the state of the HPx_SLOT straps for this interface.
1
0 = Strap is 000
1 = Strap is 001 through 111
0
EN133. This bit indicates the state of the Px_EN133 strap for this interface.
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Intel^® 82870P2 P64H2 Datasheet