82870P2P64H2 Datasheet, PDF (192/217 Pages) –

Electrical Characteristics
R
5.2.1.2
PCI Clock Uncertainty
The maximum allowable clock skew including jitter is 1 ns. This specification applies not only at a
single threshold point, but also at all the points on the clock edge that fall in the switching range
defined in Table 79 and Figure 19. The maximum skew is measured between any two components,
not between connectors.
Note:
The system designer must address an additional source of clock skew. This clock skew occurs
between two components that have clock input trip points at opposite ends of the V_IL – V_IH range.
In certain circumstances, this can add to the clock skew measurement as described here. In all
cases, total clock skew must be limited to the specified number.
Table 79. PCI Clock Skew Parameters (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%,
Tcase=0qC to 105qC)
Symbol
66 MHz 3.3 V Signaling
33 MHz 3.3 V Signaling
Units
Vtest
0.4 VCC
0.4 VCC
V
Tskew
1 (max)
2 (max)
ns
Figure 19. PCI Clock Skew
Clock @ Device 1
Clock @ Device 2
V_ih
V_il
T_skew
T_skew
V_ih
V_il
V_test
T_skew
V_test
PCIX_clk_uncertainty
192
Intel^® 82870P2 P64H2 Datasheet