82870P2P64H2 Datasheet, PDF (138/217 Pages) –

Functional Description
R
not been serviced (acknowledged), a single change in the state of an input could occur and be
posted (or buffered). The buffered value of this bit cannot be observed until the prior interrupt is
acknowledged.
Non-interrupting inputs follow at bytes 4–15. The P64H2 continually scans bytes 4–7 and stores
this data in the Hot plug Non-Interrupt Input Register. The timing of non-interrupt input scanning
for bytes 4–7 is identical to that of interrupt-capable inputs. Since scan timing cannot be easily
predicted, the memory register bit MCNF[12] status bit allows software to determine when an
eight-byte scan sequence is complete.
The current state of any of the inputs from bytes 0–15 can also be read one byte at a time through
the Serial Input Byte Pointer and Data Registers. When the byte pointer is written, the P64H2's
next scan in sequence continues shifting data in, until the appropriate byte is latched in the data
port. When the Serial Input Byte Pointer has been written, the Serial Input Busy Status bit
indicates when shifting of the selected input byte is complete. The value read from the data port is
unpredictable if it is read before shifting is complete. Bytes 8–15 can be accessed only using the
Serial Input Byte Pointer and Data port. Note that bytes 8–15 are not stuttered during scan in.
The shift clock frequency is a divide by 8 of the hub interface clock used to clock the hot plug
unit, and is approximately 8.25 MHz. External shift registers are loaded when HP_SIL# is
asserted. Shift registers can be loaded either synchronously or asynchronously. They are clocked
on the rising edge of the shift clock (HP_SIC). The serial data input pin (HP_SID) to the P64H2 is
sampled on the succeeding rising edge of the HP_SIC.
Slot Switch
The presence of logic 0 on these pins indicates that the slot is closed and can be powered on. A
logic 1 indicates that the slot should immediately be powered off. The P64H2, if enabled, auto-
powers down any slot whose switch input changes from 0 to 1, if the slot is currently powered on.
The P64H2 also powers off the LEDs for that slot.
Slot Fault
The power fault input is connected to an external device for each slot that provides the following
functions:
• Limits in-rush current to the slot so that common power rails supplying power to other slots
and system board devices do not droop or glitch as slot power is switched on.
• Detects over-current, under-voltage, and over-voltage conditions on each supply rail.
• Immediately removes power from the slot when a fault is detected so that the power supply to
other system components and slots is not adversely affected.
• Immediately isolates the slot from the bus and resets the slot so that input protection diodes on
the un-powered card do not present an excessive load on bus signals. This function is
controlled by the P64H2 when operating in one of the Parallel Modes.
• Indicates faults to the P64H2 by driving the respective slot fault pin to logic 0.
When P64H2 detects a slot fault, either on the input serial stream, or the parallel mode fault inputs,
the internal power fault latches will latch this event for each slot. The internal power fault latches
will always latch the power fault inputs, regardless of the state of SPFLE in the MCNF Register in
138
Intel^® 82870P2 P64H2 Datasheet