82870P2P64H2 Datasheet, PDF (139/217 Pages) –

Functional Description
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memory space. If power faults are disabled via the PFE bit in the MCNF Register (memory or PCI
configuration space), the power fault latches will never see power fault events.
The HMIC Register can be programmed to reflect either the slot power fault inputs (parallel or
serial), or the output of the internal power fault latches. This is done by setting/clearing the SPFLE
bit in the MCNF Register in memory space.
The internal power fault latches can be reset by either removing power from the appropriate slot,
or by clearing the PFE bit (this clears all power fault latches).
When running in 1-slot or 2-slot parallel mode, the parallel mode power fault inputs are
immediately latched by the internal power fault latches. The outputs of these latches are then used
to asynchronously disconnect the slot power, bus enable, and clock enable, as well as assert the
slot reset. This “gating logic” remains active as long as the internal power fault latch is active.
These latches can be cleared by software initiating a slot disable cycle, thus disconnecting power
to the slot and thus clearing the power fault latch. A slot disable cycle can also be initiated by
hardware via an auto power down event caused by opening a slot switch.
Downstream cycles targeting a PCI bus segment during a hot plug device’s power fault event on
that bus could cause a system hang if the slot is not yet disabled by the hot plug controller. The hot
plug controller should initiate a slot disable cycle (via software or hardware) to disable the slot and
clear the power fault latches before any cycles are allowed to run on the PCI bus.
Note:
The power fault latches can be cleared by clearing the PFE bit and this will cause the “gating
logic” to be removed. This will cause the slot power, bus enable, clock enable to all be
asynchronously enabled, and the slot reset asynchronously disabled. This is not desired behavior
and should be avoided.
PRSNT#[2:1]
These pins are provided so that software can detect the presence of a board and keep a tally of the
total amount of power used by hot plug slots. They can generate an interrupt when they change
state.
M66EN
In hot plug systems, M66EN is slot-specific. When HPx_SLOT[2:0] is not 000, the system
initially powers up at 33 MHz, and all hot plug slots are scanned by system software. If the
M66EN bits are all high for the closed slots, then software can reset the system for 66 MHz
operation, and turn on power to the cards.
PCIXCAP1/2
PCIXCAP1 and 2 represent a “serialized” version of the three-state PCIXCAP pin present on each
slot. PCIXCAP1 represents whether the PCIXCAP pin was ground or not ground (i.e., PCI-X
capable), and PCIXCAP2 represents whether the PCIXCAP pin was low (66 MHz only) or high
(133 MHz capable). The system initially powers up at 33 MHz PCI, and all hot plug slots are
scanned. If the system is capable, the bus is reset to run in the appropriate PCI-X mode.
Intel^® 82870P2 P64H2 Datasheet
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