82870P2P64H2 Datasheet, PDF (47/217 Pages) –

Register Description
R
3.2.16
PREF_MEM_BASE_UPPER—Prefetchable Memory Base
Upper 32 Bit Address Register (D29,31: F0)
Offset:
28–2Bh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
This defines the upper 32 bits of the prefetchable address base register.
Bits
Description
31:0
Prefetchable Memory Base Upper Portion (PMBU). All bits are read/writeable; the Intel®
P64H2 supports full 64-bit addressing.
3.2.17
PREF_MEM_LIM_UPPER—Prefetchable Memory Limit
Upper 32 Bit Address Register (D29,31: F0)
Offset:
2C–2Fh
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
This defines the upper 32 bits of the prefetchable address limit register.
Bits
Description
31:0
Prefetchable Memory Limit Upper Portion (PMLU). All bits are read/writeable; the Intel®
P64H2 supports full 64-bit addressing.
3.2.18
IOBLU16_ADR—I/O Base and Limit Upper 16 Bit Address
Register (D29,31: F0)
Offset:
30–33h
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
Since I/O is limited to 64 KB, this register is reserved and not used.
Bits
Description
31:16
15:0
I/O Base High 16 Bits (IOBH). Reserved
I/O Limit High 16 Bits (IOLH). Reserved
Intel^® 82870P2 P64H2 Datasheet
47