82870P2P64H2 Datasheet, PDF (189/217 Pages) –

Electrical Characteristics
R
5.2
AC Characteristics and Timing
5.2.1 PCI Interface Timing
Table 77. PCI Interface Timing (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%, Tcase=0qC to 105qC)
66 MHz
33 MHz
Symbol
Tval
Tval(ptp)
Ton
Toff
Tsu
Tsu(ptp)
Th
Trst
Trst-clk
Trst-off
Trrsu
Trrh
Trhfa
Trhff
Parameter
Min
Max
Min
Max
Units Notes
PxPCLKO[6:0] to Signal Valid Delay- bused
2
6
signals
PxPCLKO[6:0] to Signal Valid Delay-point-to-
2
6
point signals
Float to Active Delay
2
Active to Float Delay
14
Input Setup Time to PxPCLKO[6:0]-Bused
3
signals
Input Setup Time to PxPCLKO[6:0]; point-to-
5
point
Input Hold Time from PxPCLKO[6:0]
0
Reset Active Time after power stable
1
Reset Active Time after PxPCLKO[6:0]
100
stable
Reset Active to output float delay
40
PxREQ64# to RSTIN# setup time
10Tcyc
RSTIN# to REQ64# hold Time
RSTIN# high to first configuration access
0
50
2²⁵
RSTIN# high to first FRAME# Assertion
5
2
2
2
7
10,12
0
1
100
10Tcyc
0
2²⁵
5
11
ns 1, 2, 6
12
ns 1, 2, 6
ns 1, 6, 7
28
ns 1, 7
ns 2, 3, 8
ns 2, 3
ns 3
ms 4
µs 4
40
ns 4, 5
ns
50
ns
clocks
clocks
NOTES:
1. SeeFigure 16. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc.
2. PxREQ[5:0]# and PxGNT[5:0]# are point-to-point signals and have different input setup times than do
bused signals. PxGNT[5:0]# and PxREQ[5:0]# have a setup of 5 ns at 66 MHz. All other signals are
bused.
3. See Figure 17.
4. If PxM66EN is asserted, PxPCLKO[6:0] is stable when it meets the requirements in the PCI Local Bus
Specification, Revision 2.2. RSTIN# is asserted and deasserted asynchronously with respect to
PxPCLKO[6:0].
5. All output drivers must be floated when RSTIN# is active.
6. When PxM66EN is asserted, the minimum specification for Tval(min), Tval(ptp)(min), and Ton may be
reduced to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when PxM66EN is
deasserted.
7. For purposes of active/float timing measurements, the Hi-Z or “off” state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification.
8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals
at the same time. Refer to the PCI Local Bus Specification for more details.
Intel^® 82870P2 P64H2 Datasheet
189