82870P2P64H2 Datasheet, PDF (80/217 Pages) –

Register Description
R
3.3.1.19
SERR—SERR Status Register (Device 31)
Offset:
48–4Ah
Default Value: 00h
Attribute:
Size:
R/WC
24 bits
Bits
Description
23
22:14
13:8
7:6
5:0
Arbiter Time-out SERR Status (ATS).
0 = No SERR was generated. (default)
1 = Indicates that a SERR was generated due to an arbitration time-out.
Note: Software clears this bit by writing a 1 to it.
Reserved
Power Fault SERR Status (PFS).
0 = These bits can be cleared by writing logic 1 to the bit. Should a conventional power fault
change interrupt also be pending for this slot, clearing the SERR status bit for the slot has
no effect on conventional PCI interrupts. (default)
1 = These 6 bits are mapped to SERR status bits for each slot and are set to logic 1 for the
respective slot (slot A is associated with the LSB) if a power fault occurs while a slot is
connected to the bus or PCI clock. For this function to be enabled, the power fault function
enable bit and the SERR on power fault bit must also be set in the memory mapped Hot
plug Miscellaneous Register.
Note: Software clears these bits by writing a 1 to it.
Reserved
Slot Switch Change Status (SCS).
0 = Clearing the SERR status bit for a slot also clears the interrupt pending latch and allows new
switch scan data to appear in the hot plug Interrupt Input and Clear Register (HMIC).
(default)
1 = These 6 bits are mapped to SERR status bits for each slot and are set to logic 1 for the
respective slot (slot A is associated with the LSB) if a switch changes state when the switch
interrupt redirect bit for that slot is also set and the associated interrupt mask bit is logic O.
Note: Software clears this bit by writing a 1 to it.
3.3.1.20
MIDX—Alternate Memory Access Index Port Register (Device 31)
Offset:
50h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
When the "Enable PCI Configuration Space Access to Hot plug Registers" bit in the
Miscellaneous Hot Plug Configuration Register is set to 1, this register becomes functional.
Otherwise, this register is reserved, read only (0s).
Bits
Description
7:2 Memory Access Index (IDX). This field contains the memory register to access by the data port.
1:0 Reserved
80
Intel^® 82870P2 P64H2 Datasheet