82870P2P64H2 Datasheet, PDF (194/217 Pages) –

Electrical Characteristics
R
3. Setup time for point-to-point signals applies to PxREQ[5:0]# and PxGNT[5:0]# only. All other signals are
bused.
4. See the timing measurement conditions in Figure 21.
5. RST# is asserted and deasserted asynchronously with respect to PxPCLKO[6:0].
6. All output drivers must be floated when RSTIN# is active.
7. For purposes of Active/Float timing measurements, the Hi-Z or "off" state is defined to be when the total
current delivered through the component pin is less than or equal to the leakage current specification
8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals
at the same time.
9. Maximum value is also limited by delay to the first transaction (Trhfa). The PCI-X initialization pattern
control signals after the rising edge of RSTIN# must be deasserted no later than two clocks before the
first PxFRAME# and must be floated no later than one clock before PxFRAME# is asserted.
10. A PCI-X device is permitted to have the minimum values shown for Tval, Tval(ptp) ,and Ton only in PCI-X
mode. In conventional mode, the device must meet the requirements specified in the PCI Local Bus
Specification, Revision 2.2 for the appropriate clock frequency.
11. Device must meet this specification independent of how many outputs switch simultaneously.
Figure 20. PCI-X Output Timing
PxPCLKO[6:0]
Output
Delay
Output
Delay
V_th
V_test
V_tl
T_val
V_tfall
T_val
V_trise
Tri-State
Output
T_on
T_off
Time_PCIX-out-measCond
Figure 21. PCI-X Input Timing
PxPCLKO[6:0]
Input
V_th
V_tl
V_test
V_th
V_test
T_su
T_h
V_tl
inputs
valid
V_test
V_max
Time_PCIX-in-measCond
194
Intel^® 82870P2 P64H2 Datasheet