82870P2P64H2 Datasheet, PDF (32/217 Pages) –

Signal Description
R
2.8
Power and Reference Voltage Signals
Table 13. Power and Reference Voltage Signals
Signal
VCC
VCC3.3
VCC1.8
VCC5REF
VSS
HI_VREF
HI_VSWING
Description
Core Reference Voltage: This is the voltage for core (1.8 V nominal).
3.3 V Reference Voltage: This is the voltage for PCI I/O (3.3 V nominal).
1.8 V Reference Voltage: This is the voltage for hub interface I/O (1.8 V nominal).
5 V Reference Voltage: This is the reference voltage for 5 V-tolerance on PCI inputs
(5.0 V nominal).
Ground: Ground for all VCC rails.
Hub Interface Reference Voltage: This is the reference voltage for the hub interface
inputs (nominally 0.350 V).
Hub Interface RCOMP Reference Voltage: This is the reference voltage for the hub
interface RCOMP circuit (nominally 0.800 V).
2.9
Pin Straps
The following signals are used for static configuration. These signals are sampled when PWROK
goes high and then return to normal usage afterward.
Table 14. Normal Functional Pin Straps
Strap Pin
PA_133EN
PB_133EN
HPA_SLOT[2:0]
HPB_SLOT[2:0]
PAGNT[5:4]
PBGNT[5:4]
PAGNT3
PBGNT3
Function
When high, bus A is capable of 133 MHz. When low, bus A is only capable of
100 MHz.
When high, bus B is capable of 133 MHz. When low, bus B is only capable of
100 MHz.
Number of hot plug slots on bus A. “000” will hide the hot plug controller from
software.
Number of hot plug slots on bus B. “000” will hide the hot plug controller from
software.
SMBus strap address.
When high, the P64H2 uses the 200 MHz differential clock. When low, Intel® P64H2
uses the 66 MHz clock.
When high, hub interface RCOMP is disabled. When low, RCOMP is enabled.
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Intel^® 82870P2 P64H2 Datasheet