82870P2P64H2 Datasheet, PDF (112/217 Pages) –

Functional Description
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4
4.1
4.1.1
Functional Description
This chapter describes the PCI and PCI-X interfaces, hot plug controller, PCI transaction ordering,
I/OxAPIC controller, and system setup. Reliability, Availability, and Serviceability (RAS) is also
described.
PCI Interface
The P64H2 has two PCI interfaces (PCI Interface A and PCI Interface B). This section describes
the PCI interface on each P64H2 Bridge. These interfaces also support PCI-X. Refer to Section
4.2 for PCI-X interface operation.
Summary of Changes
The PCI interface of the 82870P2 P64H2 is similar to the PCI interface for the 82806AA P64H.
P64H2 enhancements include:
• 64-bit addressing outbound, with the capability to assert Dual Address Cycles (DAC).
• Full 64 bit addressing inbound from 44 bits on P64H.
• Inbound packet size based upon cache line size of the platform.
• I/O space can be programmed to 1 KB granularity through the EN1K bit of the CNF Register.
• If inbound reads are retried, they will be moved to the side so that posted writes and
completion packets can pass.
• I/O reads and writes on PCI will no longer be forwarded to the hub interface, nor will they be
forwarded to the other PCI interface.
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Intel^® 82870P2 P64H2 Datasheet