82870P2P64H2 Datasheet, PDF (92/217 Pages) –

Register Description
R
3.3.2.12
SPE—Slot Power Enable Register
Offset:
2Dh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
These bits enable and disable slot power by controlling the states of PWREN. If this register has
been changed before the Serial Output Go bit in the MCNF Register in memory space is set, a one-
pass sequence is used to set the appropriate states of the PWREN.
The state of this register is stored each time the Serial Output Go (SOGO) bit in the MCNF
Register is set. If the stored value of one of these bits changes from 0 to 1 when SOGO is set,
PWREN for that slot is set. If a stored bit changes from 1 to 0, PWREN for that slot is cleared.
The current value of this register can be read back at any time, but may not indicate the current
state of the slots if the SOGO bit has not yet been written. After SOGO is written and has been
cleared by the controller, the state of this register will indicate the power state of all the slots.
Note that the bits that pertain to disabled slots (not enabled by HPx_SLOT[2:0] power on straps)
will reflect the value of the last enabled slot. For example, if slots 3, 4, 5, 6 are disabled, their
corresponding bits in this register will match the bit value for slot 2.
Another behavior to note is that writes to disable slots via the Slot Enable register at memory
offset 01h will also clear corresponding slot bits in this register. However, writes to this register
will not modify corresponding slot bits in the Slot Enable Register. Also writes of 0 to this register
are blocked if the slot has already been fully powered on and connected to the PCI bus.
This register is normally used by software to apply power to a card to determine its PCI-X
capabilities (via the card’s M66EN and PCIXCAP pins). Writes to this register should be followed
by writes to the Slot Enable register once software has determined the M66EN and PCIXCAP pin
values for newly inserted cards. After this register is written and followed by a SOGO write, the
on/off state machine will run a one-pass sequence to apply power to the card. Note that the
controller will wait 500 ms before clearing the SOGO bit, giving the new card’s power supply time
to stabilize. However, this 500 ms timer is not functional for successive writes to the SPE Register.
After software writes to SPE and then to SOGO, software is required to then write to the SE
Register and then SOGO to connect the new cards if they are capable of running on the PCI-X bus.
If a card is not capable of running on the PCI-X bus, then software should write to SPE and SOGO
to power it down. Software should not perform a second SPE/SOGO write combination to power
up a second card immediately after the first SPE/SOGO writes - the 500 ms timer will not be
functional at this point.
Bits
Description
7:6 Reserved. Read only
Enable Power (EP).
0 = Disable. (default)
5:0 _{1 = Enable. When set, the slot is to be powered. Bit 5 corresponds to slot F, bit 4 to slot E, etc.}
until bit 0, which corresponds to slot A. These bits are R/W only for slots enabled by the
HPx_SLOT[2:0] power on straps. Otherwise, they are RO for the disabled slots. These bits
are also RO for a slot when it’s associated switch input is in an open state.
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Intel^® 82870P2 P64H2 Datasheet