82870P2P64H2 Datasheet, PDF (24/217 Pages) –

Signal Description
R
Signal
PBM66EN
PB_133EN
PBPCIXCAP
PBPLOCK#
Type
Description
66 MHz Enable: This input signal from the PCI bus indicates the speed of the
PCI bus. If it is high then the bus speed is 66 MHz and if it is low, the bus
speed is 33 MHz. This signal will be used to generate the appropriate clock
(33 MHz or 66 MHz) on the PCI bus.
If Hot plug is enabled, the PCI bus will power-up as 33 MHz PCI and the
I/O P64H2 will drive this pin low. Also, if software writes 00 to the PFREQ Register,
the P64H2 will drive this pin low.
If Hot plug is not enabled at power-up or if software never writes 00 to the
PFREQ Register, the P64H2 tri-states this pin. Additionally, if the hot plug
mode is single slot with no glue, the P64H2 tri-states this pin, regardless of the
setting of the PFREQ Register. The system board will pull this pin to a logic 1.
Enable PCI-X at 133MHz for PCI Bus B: This pin, when high, allows the
I
PCI-X segment to run at 133 MHz when PBPCIXCAP is sampled high. When
low, the PCI-X segment will only run at 100 MHz when PBPCIXCAP is sampled
high.
I
PCI-X Capable: Indicates whether all devices on the PCI bus are PCI-X
devices, so that the P64H2 can switch into PCI-X mode.
PCI Lock: This signal indicates an exclusive bus operation and may require
multiple transactions to complete. The P64H2 asserts PLOCK# when it is
O doing exclusive transactions on PCI. PLOCK# is ignored when PCI masters
are granted the bus. The P64H2 does not propagate locked transactions
upstream.
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Intel^® 82870P2 P64H2 Datasheet