 English |
|
|
|
|
|
|
|
| 82870P2P64H2 Datasheet, PDF (131/217 Pages) – | |||
| |||
| ◁ |
Functional Description
R
The following sections describe the behavior of the P64H2 on both the hub interface and PCI/PCI-
X Bus under various termination conditions. For specific information as to why the P64H2âs PCI,
PCI-X, or hub interface generates a specific termination, see the specific sections on the interface
above.
4.2.15.1 Behavior of Hub Interface Initiated Cycles to PCI/PCI-X Receiving
Immediate Terminations
The behavior described for completion required cycles is independent of the setting of the Master
Abort Mode bit and is independent of whether the cycle is exclusive (locked) or not. The P64H2
will return all 1s on data bytes for a read completion that terminates in either Master Abort or
Target Abort.
Table 32. Immediate Terminations of Completion Required Cycles to PCI/PCI-X
PCI/PCI-X
Termination
Successful
Mater Abort
Target Abort
Hub Interface Completion
Status Register Bits Set
Successful
Master Abort
Target Abort
Mater Data Parity Error (Sec) 1
Received Mater Abort (Sec)
Received Target Abort (Sec)
Signaled Target Abort (Pri)
Master Data Parity Error (Sec) 1
NOTES:
1. The Master Data Parity Error bit is set only if a data parity error was encountered on the PCI/PCI-X Bus.
Table 33. Immediate Terminations of Posted Write Cycles to PCI/PCI-X
PCI/PCI-X
Termination
MAM Bit
Hub Interface
Cycle
Status Register Bits Set
Successful
N/A
Master Abort
1
None
Do_SERR 1
None
Received Master Abort (Sec)
Signaled System Error (Pri) 1
Master Abort
0
Target Abort
N/A
None
DO_SERR 1
Received Master Abort (Sec)
Received Target Abort (Sec)
Signaled System Error (Pri) 1
NOTES:
1. The DO_SERR cycle and setting of the Signaled System Error bit only occur if the SERR#
enabled in the Primary Command Register is set.
Intel® 82870P2 P64H2 Datasheet
131
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese