82870P2P64H2 Datasheet, PDF (156/217 Pages) –

Functional Description
R
4.5
Transaction Ordering
4.5.1 Comparison of Rules vs A PCI–PCI Bridge
When a PCI segment is in PCI (PCI-X) mode, the P64H2 follows the producer-consumer model of
a PCI – PCI bridge. Table 49 is taken from Appendix E of the PCI Local Bus Specification,
Revision 2.2 for PCI, and Section 8.4.4 of the PCI-X Addendum to the PCI Local Bus
Specification, Revision 1.0. The “bolded” entries represent differences from that table, and an
explanation of the differences.
Table 49. Ordering Rules for a PCI-PCI Bridge
Row pass Col?
Posted Write
Delayed (Split)
Read Request
Delayed (Split)
Write Request
Delayed (Split)
Read Completion
Delayed (Split)
Write Completion
Posted
Write
No
No
Delayed
(Split) Read
Request
Yes
Yes^A No^C
Delayed
(Split) Write
Request^D
Yes
Yes^A No^C
Delayed
(Split) Read
Completion
Yes
No^C Yes^C
Delayed (Split)
Write
Completion^D
Yes
Yes^B
Yes^C
No
No^C
No^C
No^D Yes^C
No^D
Yes^C
No
Yes
Yes
No^C Yes^C
No^C
Yes^C
No^C
Yes
Yes
No^C Yes^C
No^C
Yes^C
Table Legend:
A. Subsequent requests only (prefetches). All inbound initial requests are in order.
B. Multiple non-posted requests from MCH must complete in order.
C. In a bridge these are allowed to be yes/no.
D. In a bridge these are allowed to be yes/no. The P64H2 will not accept inbound write
requests that are not posted (I/O writes, configuration writes).
4.5.2
Ordering Relationships
Ordering relationships are established for the following classes of transactions crossing the
P64H2:
• The P64H2 does not combine separate write transactions into a single write transaction.
• The P64H2 does not merge bytes on separate write transactions to the same DWord address.
• The P64H2 does not collapse sequential write transactions to the same address into a single
write transaction – the PCI Local Bus Specification, Revision 2.0 does not permit this
operation.
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Intel^® 82870P2 P64H2 Datasheet