82870P2P64H2 Datasheet, PDF (42/217 Pages) –

Register Description
R
3.2.7
3.2.8
3.2.9
42
CLS—Cache Line Size Register (D29,31: F0)
Offset:
0Ch
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register indicates the cache line size of the system.
Bits
Description
7:0 Cache Line Size (CLS). The value in this field is used by the Intel® P64H2 to determine the size
of packets on the hub interface. This read/write register specifies the system cacheline size in
units of DWords.
08h = 32-byte line (8 DWords).
10h = 64-byte line
20h = 128-byte line.
Any value outside this range will default to a 64-byte line. When the P64H2 is creating read and
write requests to the hub interface, this value is used to partition the requests such that multiple
snoops for the same line are avoided in the memory subsystem.
PMLT—Primary Master Latency Timer Register
(D29,31: F0)
Offset:
0Dh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register does not apply to the hub interface and is maintained as R/W for software
compatibility.
Bits
Description
7:3 Time Value (TV). Read / write used for software compatibility only.
2:0 Reserved
HEADTYP—Header Type Register (D29,31: F0)
Offset:
0Eh
Default Value: 01h
Attribute:
Size:
RO
8 bits
This register determines how the rest of the configuration space is laid out.
Bits
Description
7
Multi-Function Device (MFD). This bit returns 0 to indicate the bridge is a single-function
device.
Header Type (HTYPE). This field defines the layout of addresses 10h through 3Fh in PCI
6:0 configuration space. This field reads as 01h to indicate that the register layout conforms to the
standard PCI-to-PCI bridge layout.
Intel^® 82870P2 P64H2 Datasheet