82870P2P64H2 Datasheet, PDF (107/217 Pages) –

Register Description
R
3.5
SMBus Interface
The SMBus interface does not have PCI configuration registers. The SMBus address is set upon
PWROK by sampling PAGNT[5:4] and PBGNT[5:4].
The SMBus controller has access to all internal registers. The generation of cycles on the hub
interface or PCI are not supported transactions, and undefined results may occur if they are
attempted. It can perform reads and writes from all registers through the particular interface’s
configuration space. Hot plug and I/OxAPIC memory spaces are accessible through their
respective configuration spaces.
The following registers are only accessible through the SMBus port.
Table 21. SMBus Register Address Map
Address
Offset
00h
01h
02h
03h
04–07h
FFh
Symbol
Name
CMDSTS
BNUM
DFNUM
RNUM
DATA
CFG
Command / Status Register
Bus Number
Device / Function Number
Register Number
Data Register
SMBus Configuration (Default = 00h)
Default
00h
00h
00h
00h
00000000h
00h
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
Intel^® 82870P2 P64H2 Datasheet
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