82870P2P64H2 Datasheet, PDF (86/217 Pages) –

Register Description
R
Bits
Description
7
Parallel Mode (PM)—RO. Hardwired to 0. This bit is irrelevant for the P64H2 and is 0 even
though the hot plug controller is sometimes operating in parallel mode.
6
Bus Frequency Range (BFR)—R/W. Not implemented. This bit is maintained as read/write for
software compatibility.
Arbitration Timer Timeout (ATT)—R/WC.
0 = No arbitration timer timeout. (default)
5
1 = The P64H2 was forced to complete a power-up or power-down cycle without getting a grant
from the arbiter.
Note: Software clears this bit by writing a 1 to it.
4
Dummy Cycle Enable (DCE). Not implemented. The P64H2 does not execute dummy cycles.
This bit is read/write for software compatibility.
Interrupt Pending (IP)—RO.
3
0 = When the interrupt is cleared, the bit is set to 0. (default)
1 = This bit is set after an interrupt is generated from the General Interrupt Inputs.
Shift Output Interrupt Pending / Clear (SOIP)—R/WC.
0 = No interrupt was generated by SOGO. (default)
2
1 = Indicates that an interrupt was generated by SOGO changing from 1 to 0 while the SOIE bit
was set.
Note: Software clears this bit by writing a 1 to it.
Shift Output Interrupt Enable (SOIE)—R/W.
1
0 = Disable. (default)
1 = Enable. An interrupt is generated when SOGO changes from 1 to 0.
Shift Output Go / Busy Status (SOGO)—R/W. Writing this bit to 1 from 0 causes the serial
outputs to be updated from the latest contents of the LED, RST#, Slot Enable, Slot Power
Enable, and General Purpose Output registers. Writing 0 to this bit or writing 1 while it is 1 has no
0
effect. (default=0)
When read, this bit indicates the busy status of the shift output logic. When 0, the output shift is
complete.
86
Intel^® 82870P2 P64H2 Datasheet