82870P2P64H2 Datasheet, PDF (126/217 Pages) –

Functional Description
R
4.2.5
Wait States
The P64H2 never generates wait states as a target; it ends the transfer.
4.2.6 Split Transactions
4.2.6.1 Completer Attributes
Table 26. Intel^® P64H2 Implementation Completion Attribute Fields
Attribute
Byte Count Modified (BCM)
Split Completion Error (SCE)
Split Completion Message (SCM)
Function
This bit is used for diagnostic purposes. The Intel® P64H2 never
sets this bit.
The P64H2 only sets this bit if a memory read command from PCI-
X master or target aborted on the hub interface.
This bit shadows the SCE bit.
4.2.6.2
Requirements for Accepting Split Completions
The P64H2 asserts PxDEVSEL# and discards the data if the Requester ID matches the bridge, but
the tag does not match that of any outstanding requests from this device, or if the byte count
exceeds that of the split request.
The hub interface accepts more than one completion required request from the hub interface, but
only one will be pending on any PCI/PCI-X interface at a time.
4.2.6.3 Split Completion Messages
The P64H2 can only generate error messages for cycles that cross the bridge that master or target
abort. No DWord cycles will cross the bridge that requires completion (i.e., I/O cycles). Therefore,
the P64H2 can only generate a “PCI-X Bridge Error” completion message for the memory read
commands as indicated in Table 27.
Table 27. Split Completion Abort Registers
Index
Message
00h Master-Abort: The Intel® P64H2 encountered a Master-Abort on the destination bus.
01h Target-Abort: The P64H2 encountered a Target-Abort on the destination bus.
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Intel^® 82870P2 P64H2 Datasheet