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82870P2P64H2 Datasheet, PDF (25/217 Pages) –
Signal Description
R
2.2
PCI Bus Interface 64-bit Extension
There are two sets of PCI Bus extension signals; one for PCI Bus A and one for PCI Bus B.
Table 4. PCI Bus Interface 64-bit Extension Interface A Signals
Signal
Type
Description
PAAD[63:32]
PAC/BE[7:4]#
PAPAR64
PAREQ64#
PAACK64#
PCI Address/Data: These signals are a multiplexed address and data bus. This
bus provides an additional 32 bits to the PCI bus. During the data phases of a
transaction, the initiator drives the upper 32 bits of 64-bit write data, or the
I/O target drives the upper 32 bits of 64-bit read data, when PAREQ64# and
PAACK64# are both asserted. When not driven, PAAD[63:00] are pulled up to a
valid logic level through external resistors. For a 5 V environment use a 2.7 kΩ
resistor, in a 3.3 V environment use an 8.2 KΩ resistor.
Bus Command and Byte Enables (Upper 4 bits): These signals are a
multiplexed command field and byte enable field. For both read and write
transactions, the initiator will drive byte enables for the PAAD[63:32] data bits
on PAC/BE[7:4]# during the data phases when PAREQ64# and PAACK64# are
I/O both asserted.
When not driven, PAC/BE[7:4]# is pulled up to a valid logic level through
external resistors. In a 5 V environment use a 2.7 kΩ resistor; in a 3.3 V
environment use a 8.2 kΩ resistor
PCI Interface Upper 32-bits Parity: This signal carries the even parity of the
I/O
36 bits of PAAD[63:32] and PAC/BE[7:4]# for both address and data phases.
When not driven, PAPAR64 is pulled up to a valid logic level through external
resistors.
PCI interface Request 64-bit Transfer: This signal is asserted by the initiator
I/O
to indicate that the initiator is requesting a 64-bit data transfer. It has the same
timing as PAFRAME#. When the Intel® P64H2 is the initiator, this signal is an
output. When the P64H2 is the target, this signal is an input.
PCI Interface Acknowledge 64-bit Transfer: This signal is asserted by the
I/O target only when PAREQ64# is asserted by the initiator. It indicates the target’s
ability to transfer data using 64 bits. It has the same timing as PADEVSEL#.
Intel® 82870P2 P64H2 Datasheet
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