82870P2P64H2 Datasheet, PDF (60/217 Pages) –

Register Description
R
3.2.33
RAS_PAL—RAS PCI Address Low Register (D29,31: F0)
Offset:
70–73h
Default Value: xxxxxxxxh
Attribute:
Size:
RO
32 bits
This register contains the low 32 bits of address from the PCI header.
Bits
Description
31:0
Address - low 32 bits (ADR). This field is only valid if the AEP, DEP, PRTA, PRMA, or DEBO
bits are set in the RAS_STS Register (60h).
3.2.34
RAS_PAH—RAS PCI Address High Register (D29,31: F0)
Offset:
74–77h
Default Value: xxxxxxxxh
Attribute:
Size:
RO
32 bits
This register contains the upper 32 bits of address from the PCI cycle.
Bits
Description
Address - High 32 bits (ADR). This field is only valid if the AEP, DEP, PRTA, PRMA, or DEBO
31:0
bits are set in the RAS_STS Register (60h). If an address parity error occurred during a single
address cycle, then these bits will be forced to 0s. Reliability Availability Serviceability software
must assume that if these bits are 0s, the cycle was a single address cycle.
3.2.35
RAS_PDL—RAS PCI Data Low 32 Bits Register
(D29,31: F0)
Offset:
78–7Bh
Default Value: xxxxxxxxh
Attribute:
Size:
RO
32 bits
This register provides the low 32 bits of data from the PCI cycle.
Bits
Description
PCI Data - low 32 bits. (DTA). This field is only valid if the AEP, DEP, PRTA, PRMA, or DEBO
31:0
bits are set in the RAS_STS Register (60h). This field will contain the 32-bit value driven during
the attribute phase on all attribute parity errors. This field is not valid for parity errors that occur
during the address phase.
60
Intel^® 82870P2 P64H2 Datasheet