82870P2P64H2 Datasheet, PDF (51/217 Pages) –

Register Description
R
3.2.22
CNF—P64H2 Configuration Register (D29,31: F0)
Offset:
40–41h
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bits
Description
15:10
9
8
7:6
5
4:3
Disable PCLKOUT [5:0] (DPCLK)—R/W.
0 = Enable.
1 = Disable. Disables a PCI clock output that is not used in the system. Bit 15 refers to
PCLKOUT5, bit 14 to PCLKOUT4, etc. When disabled, the PCLKOUT pin is tri-stated.
Enable I/O Space to 1 KB Granularity (EN1K)—R/W.
0 = Disable
1 = Enable. I/O space is decoded to 1 KB instead of the 4 KB limit that currently exists in the I/O
base and I/O limit registers. It does this by redefining bits [11:10] and bits [3:2] of the
IOBL_ADR Register (offset 1Ch) to be read/write, and enables them to be compared with
the I/O address bits [11:10] to determine if they are within the bridge’s I/O range.
PCI Mode (PMODE)—R/W.
0 = Bus is in PCI mode.
1 = Bus is operating in PCI-X mode.
PCI Frequency (PFREQ)—R/W. This field determines the frequency the PCI bus operates. After
software determines the busses capabilities, it sets this value and the PMODE (bit 8 of this
register) to the desired frequency and resets the PCI bus.
00 = 33 MHz (Only valid if PMODE is 0)
01 = 66 MHz
10 = 100 MHz (Only valid if PMODE is 1)
11 = 133 MHz (Only valid if PMODE is 1)
Invalid combinations should not be written by software. Results will be indeterminate.
Restreaming Disable (RSDIS)—R/W.
0 = Enable.
1 = Disable. This bridge of the P64H2 will no longer perform restreaming. This bit only applies
when the bridge is in PCI mode, and not when the bridge is in PCI-X mode. When the PCI
transaction ends, either due to a PCI master removing PxFRAME# or the P64H2 asserting
PxSTOP#, the P64H2 will discard all data in the prefetch buffer.
Prefetch Policy (PP)—R/W. This field controls how the P64H2 prefetches data on behalf of PCI
masters.
0x = Allow prefetching on memory read multiple (MRM)
1x = Disable all prefetching
Intel^® 82870P2 P64H2 Datasheet
51