82870P2P64H2 Datasheet, PDF (66/217 Pages) –

Register Description
R
3.2.46
PCC—PCI Delay Compensation Control Register
(D29,31: F0)
Offset:
E4–E5h
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
This register controls PCI buffer delay compensation. There is one register per PCI interface.
Bits
Description
15:14
13:12
11:10
9
8
7:0
Oscillator Control (OSC). This field controls the compensation delay oscillator.
Compensation Decoder Shift (CDS). This field shifts the output of the compensation decoder.
00 = No shift (default)
01 = Increase delay by 1
10 = Increase delay by 2
11 = Decrease delay by 1
PCI-X Bias Control (XBC). This field controls PCI-X Capability Detect Biases.
00 = No Shift (default)
01 = Lower references
10 = Increase references
11 = Further increase
Compensation Disable (CD). This bit disables the compensation logic.
0 = Enable
1 = Disable
Bypass Enable (BE). This bit enables the bypass values in bits [7:0] of this register to be used
instead of the internally generated compensation value.
0 = Disable
1 = Enable
Bypass Value (BV). This field contains the bypass value to be used to override the internal
compensation value when bypass is enabled through bit 8 of this register (the Bypass Enable
bit). When the Bypass Enable bit is 0, a read of these bits reflect the current state of the
compensation circuit.
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Intel^® 82870P2 P64H2 Datasheet