82870P2P64H2 Datasheet, PDF (102/217 Pages) –

Register Description
R
3.4.2.3
3.4.2.4
PAR—IRQ Pin Assertion Register (D28,30: F0)
Offset:
20h
Default Value: xxh
Attribute:
Size:
R/W
8 bits
The IRQ Pin Assertion Register is present to provide a mechanism to scale the number of interrupt
inputs into the I/Ox APIC without increasing the number of dedicated input pins. When a device
that supports this interrupt assertion protocol requires interrupt service, that device will issue a
write to this register. Bits [4:0] written to this register contain the IRQ number for this interrupt.
The only valid values are 0–23.
Bits
Description
7:0 Assertion (PAR). Virtual pin to be asserted (active high).
EOI—End of Interrupt Register (D28,30: F0)
Offset:
40h
Default Value: xxh
Attribute:
Size:
WO
8 bits
The EOI register is present to provide a mechanism to maintain the level triggered semantics for
level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/OxAPIC will check the lower 8 bits written to this
register, and compare it with the vector field for each entry in the I/O Redirection Table. When a
match is found, the Remote_IRR bit for that I/O Redirection Entry is cleared.
Note that if multiple I/O Redirection entries, for any reason, assign the same vector for more than
one interrupt input, each of those entries will have the Remote_IRR bit reset to 0.
Bits
Description
7:0 End of Interrupt (EOI). Vector to be cleared by the EOI.
102
Intel^® 82870P2 P64H2 Datasheet