82870P2P64H2 Datasheet, PDF (75/217 Pages) –

Register Description
R
3.3.1.12
INTR—Interrupt Information Register (Device 31)
Offset:
3C–3Dh
Default Value: 0100h
Attribute:
Size:
R/W, RO
16 bits
This register contains information about how the P64H2 hot plug controller generates interrupts.
Note that internally, the controller interrupt is connected to the IRQ23# input of the APIC on the
same bus (A or B).
Bits
Description
15:8
Interrupt Pin (IPIN)—RO. This field indicates that the hot plug controller generates the INTA#
pin.
7:0
Interrupt Line (ILINE)—R/W. This field is programmed to indicate which interrupt line (vector)
the interrupt is connected to. No hardware action is taken on this register.
3.3.1.13
SID—Slot ID Register (Device 31)
Offset:
40h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register indicates which slots in the system support hot plug. This register is aliased with a
register of the same name in memory space. No hardware action is taken by these bits.
Bits
Description
7:4
Lowest Device Number (DEV). This field provides the PCI device number for the first slot that
supports hot plug.
3:0
Number of Hot Plug Slots (NUM). This field provides the number of hot plug slots in the
system.
3.3.1.14
HPFC—Hot Plug Frequency Control Register (Device 31)
Offset:
41h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bits
Description
7:4 Reserved. This field is R/W for software compatibility
3
Reserved. Read only
2:0
Frequency Select (FS). The Intel® P64H2 hot plug controller always uses a 66 MHz core clock
for its timings. These register bits are maintained as R/W for software compatibility.
Intel^® 82870P2 P64H2 Datasheet
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