82870P2P64H2 Datasheet, PDF(68/217 Page)

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82870P2P64H2 Datasheet, PDF (68/217 Pages) –

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3.2.48 Prefetch Control Registers

The four prefetch control registers contain prefetch parameters. Each parameter is in 64-byte cache

line quantities. BIOS programs the values in these registers on power up. The values in the

registers are 0-based where a 0000b means 64 bytes, a 0001b means 128 bytes, etc.

Note:

There is a fifth parameter in the prefetch algorithm called âDâ. D is the delay to wait before

sending a Subsequent Request (RS) if prior Subsequent Requests (RS) still have not brought the

prefetch buffers above the Subsequent Threshold (TS). Its value is in PCI clocks and is the RS

field in the prefetch control registers with the value 111 appended to the beginning of the number

(i.e., RS:111). For example, IF RS = 0101b, then D = 0101111b.

Note:

For Memory Read (MR) and Memory Read Line (MRL) commands in PCI, no prefetching is

performed. A fetch of 1 cache line (based on the cache line size register) is performed and when it

drains, the delayed transaction is complete. A new delayed transaction will be established if the

master wished the burst to continue.

3.2.48.1

PC33âPrefetch Control for 33 MHz Register (D29,31: F0)

Offset:

F8âF9h

Default Value: 1212h

Attribute:

Size:

R/W

16 bits

Bits

Description

15:12

11:8

7:4

3:0

Subsequent Threshold (TS). This field represents the subsequent threshold size in 64-byte

cache lines.

Subsequent Request (RS). This field represents the subsequent request size in 64-byte cache

lines.

Initial Threshold (TI). This field represents the initial threshold size in 64-byte cache lines.

Initial Request (RI). This field represents the initial request size in 64-byte cache lines.

3.2.48.2

PC66âPrefetch Control for 66 MHz Register (D29,31: F0)