82870P2P64H2 Datasheet, PDF (120/217 Pages) –

Functional Description
R
4.1.9.1
Address Parity Errors
The P64H2 checks address parity for all transactions on both the hub interface and PCI buses, for
all address and all bus commands. Address parity errors are very serious and may abort further
data transfers, depending on the direction of the transfer and the setting of the Parity Error
Response bit (PD_STS Register).
When the P64H2 detects a parity error or multiple-bit ECC error in the header section of a hub
interface packet, it:
• Sets the Detected Parity Error bit (bit 15) in the PD_STS Register (offset 06–07h) if the
address is targeting the device. The bridge devices will log address parity errors independent
of the target address.
• Initiates the DO_SERR special cycle, and sets the signaled system error bit (bit 14) in the
PD_STS Register (offset 06–07h), if the Parity Error Response bit (bit 6) in the PCI Device
Command Register (PD_CMD, offset 04–05h) is set and SERR# is enabled.
• Will attempt to interpret the cycle as best as it can and will forward it with an address parity
error tag to the internal logic where it will abort internally. If a device is not enabled to
respond to parity errors, it will ignore the address parity error (except for setting the Detected
Parity Error bit) and if the address targets that device, accept the cycle and respond as if there
was no address parity error. The cycle will be forwarded to PCI with good address parity if
the cycle targets a bridge and it is not enabled to respond to parity errors.
If a single bit ECC error is detected during the header section, it is corrected and none of the above
occurs.
When the P64H2 detects an address parity error on the PCI interface, the following events occur:
• The P64H2 sets the detected parity error bit (bit 15) in the Secondary Status Register
(offset 1E–1Fh).
• If the parity error response bit (bit 0) is 0 in the Bridge Control Register (offset 3E–3Fh), the
address parity errors are ignored. The cycles would be treated as if no error was observed.
• If the parity error response bit is set and the address parity error is observed on memory
cycles, then the cycle is accepted as if the address was correct; Delayed Transactions
established for memory reads and data posted for memory writes. The cycles are forwarded to
the hub interface with correct address parity.
The P64H2 initiates the DO_SERR special cycle on the hub interface and sets the signaled system
error bit in the PCI Primary Device Status (PD_STS) Register, if all of the following conditions
are met:
• The SERR# enable bit is set in the PCI Primary Device Command Register.
• The parity error response bit is set in the Bridge Control Register.
• The SERR# enable bit is set in the Bridge Control Register.
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Intel^® 82870P2 P64H2 Datasheet