82870P2P64H2 Datasheet, PDF (36/217 Pages) –

Register Description
R
3.2
Hub Interface-to-PCI Bridge PCI Configuration
Registers (Device 31 and 29)
Table 15 lists the registers contained in this section. The register descriptions that follow are
arranged by address as indicated in Table 15.
Note: The Hub Interface-to-PCI Bridge does not perform function decode.
Table 15. Hub Interface-to-PCI Bridges Address Map (D31,29, F0)
Address
Offset
00–01h
02–03h
04–05h
06–07h
08h
09–0Bh
0Ch
0Dh
0Eh
18–1Ah
1Bh
1C–1Dh
1E–1Fh
20–23h
24–27h
28–2Bh
2C–2Fh
30–33h
34h
35–3Bh
3C–3Dh
3E–3Fh
40–41h
42h
44–47h
48–4Fh
Symbol
Register Name
VID
DID
PD_CMD
PD_STS
RID
CC
CLS
PMLT
HEADTYP
BNUM
SMLT
IOBL_ADR
SECSTS
MBL_ADR
PMBL_ADR
PREF_MEM_
BASE_UPPER
PREF_MEM_
LIM_UPPER
IOBLU16_ADR
CAPP
—
INTR
BRIDGE_CNT
CNF
MTT
STRP
—
Vendor Identification
Device Identification
PCI Primary Device Command
PCI Primary Device Status
Revision Identification
Class Code
Cache Line Size
Primary Master Latency Timer
Header Type
Bus Number
Secondary Master Latency Timer
I/O Base and Limit Address
Secondary Status
Memory Base and Limit Address
Prefetchable Memory Base and Limit
Address
Prefetchable Memory Base Upper 32 Bit
Address
Prefetchable Memory Limit Upper 32 Bit
Address
I/O Base and Limit Upper 16 Bit Address
Capabilities List Pointer
Reserved
Interrupt Information
Bridge Control
Intel P64H2 Configuration
Multi-Transaction Timer
PCI Strap Status
Reserved
Default
8086h
1460h
0000h
0030h
04h
060400h
00h
00h
01h
000000h
00h
0000h
02A0h
00000000h
00010001h
Access
RO
RO
R/W
R/W
RO
RO
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
00000000h
R/W
00000000h
R/W
00000000h
RO
05h
RO
—
—
0000h
RO
0000h
R/W
0000h
R/W
00h
R/W
00000000h
RO
—
—
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Intel^® 82870P2 P64H2 Datasheet