82870P2P64H2 Datasheet, PDF (11/217 Pages) –

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Tables
Table 1. Hub Interface ...................................................................................................... 21
Table 2. PCI Bus Interface A Signals................................................................................ 21
Table 3. PCI Bus Interface B Signals................................................................................ 23
Table 4. PCI Bus Interface 64-bit Extension Interface A Signals...................................... 25
Table 5. PCI Bus Interface 64-bit Extension Interface B Signals...................................... 26
Table 6. PCI Bus Interface Clocks and Reset Interface A Signals ................................... 27
Table 7. PCI Bus Interface Clocks and Reset Interface B Signals ................................... 27
Table 8. Interrupt Interface Signals................................................................................... 29
Table 9. Hot Plug Interface A Signals ............................................................................... 29
Table 10. Hot Plug Interface B Signals ............................................................................. 30
Table 11. SMBus Interface Signals................................................................................... 31
Table 12. Miscellaneous Signals ...................................................................................... 31
Table 13. Power and Reference Voltage Signals ............................................................. 32
Table 14. Normal Functional Pin Straps ........................................................................... 32
Table 15. Hub Interface-to-PCI Bridges Address Map (D31,29, F0) ................................ 36
Table 16. Hot Plug Controller PCI Configuration Address Map (Device 31)..................... 70
Table 17. Hot Plug Controller Memory Space Register Map ............................................ 83
Table 18. I/OxAPIC PCI Configuration Space Register Map ............................................ 94
Table 19. I/OxAPIC Memory Space Register Map ......................................................... 101
Table 20. I/OxAPIC Indirect Memory Space Register Address Map .............................. 103
Table 21. SMBus Register Address Map........................................................................ 107
Table 22. Intel^® P64H2 PCI Transactions....................................................................... 113
Table 23. Command Encoding ....................................................................................... 124
Table 24. Intel® P64H2 Implementation of Requester Attribute Fields .......................... 125
Table 25. DEVSEL# Timing ............................................................................................ 125
Table 26. Intel^® P64H2 Implementation Completion Attribute Fields.............................. 126
Table 27. Split Completion Abort Registers .................................................................... 126
Table 28. M66EN and PCIXCAP Encoding .................................................................... 128
Table 29. PCI-X Initialization Pattern .............................................................................. 128
Table 30. Conventional PCI to PCI-X / Hub Interface..................................................... 129
Table 31. PCI-X to Conventional PCI (peer) / Hub Interface.......................................... 130
Table 32. Immediate Terminations of Completion Required Cycles to PCI/PCI-X ......... 131
Table 33. Immediate Terminations of Posted Write Cycles to PCI/PCI-X ...................... 131
Table 34. Split Terminations of Completion Required Cycles to PCI-X .......................... 132
Table 35. Response to PCI-X Split Completions ............................................................ 133
Table 36. Terminations of Completion Requited Cycles to Hub Interface ...................... 133
Table 37. Stutter Logic Modes ........................................................................................ 136
Table 38. Shift Register Data.......................................................................................... 140
Table 39. Serial Mode Output Shift-Out SR Bit Order .................................................... 142
Table 40. Power Up Timings (CBF Mode) ...................................................................... 143
Table 41. Power Down Timings (CBF Mode) ................................................................. 144
Table 42. Power Up Timings (CBL Mode) ...................................................................... 145
Table 43. Power Down Timings (CBL Mode).................................................................. 146
Table 44. Registers Not Reset with a Secondary Bus Reset.......................................... 146
Table 45. Hot Plug Mode Settings .................................................................................. 148
Table 46. Hot Plug Mode Signals.................................................................................... 149
Table 47. Hot Plug Mode Reset Values .......................................................................... 149
Table 48. PCI Functions/Devices Table.......................................................................... 155
Table 49. Ordering Rules for a PCI-PCI Bridge .............................................................. 156
Table 50. Immediate Terminations of Completion Required Cycles to PCI/PCI-X ......... 157
Intel^® 82870P2 P64H2 Datasheet
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