82870P2P64H2 Datasheet, PDF (196/217 Pages) –

Electrical Characteristics
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5.2.2.2 PCI-X Clock Uncertainty
The maximum allowable clock uncertainty including jitter is shown in Table 82 and Figure 23.
This specification applies, not only at a single threshold point, but also at all points on the clock
edge between V_IL and V_IH. For add-in cards, the maximum skew is measured between component
pins not between connectors.
Table 82. PCI-X Clock Uncertainty Parameters (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%,
Tcase=0qC to 105qC)
Symbol
PCI-X
Vtest-clk
Tskew
0.4VCC
0.4 (max)
Conventional
PCI 66 (ref)
0.4VCC
0.8 (max)
3.3 V Signaling Conventional
PCI 33 (ref)
0.4VCC
1.6 (max)
Units
V
ns
Figure 23. PCI-X Clock Skew
Clock @ Device 1
Clock @ Device 2
V_ih
V_il
T_skew
T_skew
V_ih
V_il
V_test
T_skew
V_test
PCIX_clk_uncertainty
196
Intel^® 82870P2 P64H2 Datasheet