82870P2P64H2 Datasheet, PDF (179/217 Pages) –

Functional Description
R
Table 61 provides valid values in the RAS_STS Register (offset 60h). All entries marked as
“invalid” mean that the event is invalid for this particular RAS_STS bit.
Table 61. RAS_STS Register (offset 60h) Values
Error Bit Set
Name Bit
HTA 13
HMA 12
PTA 11
PRMA 10
AEHS 9
DEHS 8
AEP
5
AEHM 4
DEBI 3
DEP
2
DEBO 1
DEHM 0
Allowable Values
HAGT (bit 20)
0, 1
0, 1
Invalid
PAGT (bits 23:21)
Invalid
Invalid
000 – 101, 111
Invalid
111
1
1
Invalid
1
Invalid
Invalid
000 – 101
Invalid
0
Invalid
Invalid
000 – 101
Invalid
111
1
Invalid
Notes
Intel® P64H2 can only receive a master abort
on PCI, it cannot generate one.
P64H2 will not generate an address parity error.
If a failure occurs internal to the P64H2 heading
towards the hub interface (or the peer PCI),
then the P64H2 is the failure agent.
P64H2 will not generate a data parity error,
unless the data is being poisoned from a failure
due to DEBO or DEHM. Therefore, the error will
already have been logged.
If a failure occurs internal to the P64H2 heading
towards PCI from the hub interface or a PCI
peer, then the P64H2 is the failure agent.
P64H2 will not generate a data parity error,
unless the data is being poisoned due to DEBI
or DEP. Therefore, the error will already have
been logged.
4.9.5
Data Poisoning
When an error is logged by the P64H2, that error will still proceed to its final interface. However,
the data shall remain poisoned throughout the transfer (except in the case of single bit ECC errors).
Therefore, a multi-bit ECC error on the hub interface will result in a parity error on PCI, a parity
error on PCI will result in a forced multi-bit ECC error on the hub interface, and an error on the
internal SRAM will cause a parity / multi-bit ECC error at its destination interface.
Intel^® 82870P2 P64H2 Datasheet
179