82870P2P64H2 Datasheet, PDF (165/217 Pages) –

Functional Description
R
ACK/NACK
For every 8 bits of data transfer (including address and direction), the receiving agent must
respond with ACK or NACK. An ACK is requires SDA = 0 during SCL = 1 (see Figure 8). A
NACK requires SDA = 1 during SCL = 1 (see Figure 9).
Figure 8. ACK (A) Signaling
SCL
SDA
SMBus_ACK
Figure 9. NACK (N) Signaling
SCL
SDA
SMBus_nack
During a write cycle, the P64H2 must drive an ACK after the address/direction phase, and after the
data phase. During a read cycle, the P64H2 must drive an ACK/NACK after the address/direction
phase, and (if ACKed) the initiator must drive an ACK/NACK after the P64H2 returns its 8 bits of
data.
Wait States
The receiver (initiator or target) can add wait states, after driving ACK for receiving the last byte,
by driving the SCL line low. Further data transfers are delayed until the receiver stops driving SCL
low. It is expected the P64H2 will drive the SCL line low after receiving data on writes until the
write is complete, and after receiving the direction bit on reads until the read data is ready.
Intel^® 82870P2 P64H2 Datasheet
165