82870P2P64H2 Datasheet, PDF (58/217 Pages) –

Register Description
R
Bits
Description
Address Parity / Multi-bit ECC Error in from the Hub Interface (AEHM)—R/WC. This bit is
only visible from device 31.
0 = No address parity / multi-bit ECC error detected.
4
1 = Packet arrived on the hub interface that had a parity / multi-bit ECC error in the command
phase (address / header).
Note: Software clears this bit by writing a 1 to it.
Inbound Data Parity from Internal Buffers (DEBI)—R/WC.
0 = No inbound data soft error detected.
3
1 = Soft error was detected in the internal buffer on data flowing inbound from a PCI cycle.
Note: Software clears this bit by writing a 1 to it.
Data Parity in from PCI (DEP)—R/WC.
0 = No data parity error calculated.
2
1 = Data parity error was calculated on an P64H2 read from PCI or a write from PCI
Note: Software clears this bit by writing a 1 to it.
Outbound Data Parity Error from Internal Buffers (DEBO)—R/WC.
0 = No outbound data soft error detected.
1
1 = Soft error occurred in the internal SRAM on data headed outbound to PCI.
Note: Software clears this bit by writing a 1 to it.
Data Parity / Multi-bit ECC Error in from the Hub Interface (DEHM)—R/WC. This bit is only
visible from device 31.
0
0 = No data parity / multi-bit ECC error detected.
1 = P64H2 received a packet on the hub interface with a data parity / multi-bit ECC error.
Note: Software clears this bit by writing a 1 to it.
58
Intel^® 82870P2 P64H2 Datasheet