82870P2P64H2 Datasheet, PDF (46/217 Pages) –

Register Description
R
3.2.14
MBL_ADR—Memory Base and Limit Address Register
(D29,31: F0)
Offset:
20–23h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
This register defines the base and limit (aligned to a 1 MB boundary) of the prefetchable memory
area of the bridge. Accesses from the hub interface that are within the ranges specified in this
register will be sent to PCI if the memory space enable bit is set.
If the bus master enable bit is set, accesses from PCI that are outside the ranges specified in this
register will be forwarded to the hub interface.
Bits
Description
31:20
19:16
15:4
3:0
Memory Limit (ML). These bits are compared with bits [31:20] of the incoming address to
determine the upper 1 MB aligned value (exclusive) of the range. The incoming address must be
less than this value.
Reserved
Memory Base (MB). These bits are compared with bits [31:20] of the incoming address to
determine the lower 1 MB aligned value (inclusive) of the range. The incoming address must be
greater than or equal to this value.
Reserved
3.2.15
PMBL_ADR—Prefetchable Memory Base and Limit
Address Register (D29,31: F0)
Offset:
24–27h
Default Value: 00010001h
Attribute:
Size:
R/W, RO
32 bits
This register defines the base and limit (aligned to a 1 MB boundary) of the prefetchable memory
area of the bridge. Accesses from the hub interface that are within the ranges specified in this
register will be sent to PCI if the memory space enable bit is set.
If the bus master enable bit is set, accesses from PCI that are outside the ranges specified in this
register are forwarded to the hub interface.
Bits
Description
31:20
19:16
15:4
3:0
Prefetchable Memory Limit (PML)—R/W. These bits are compared with bits [31:20] of the
incoming address to determine the upper 1 MB aligned value (exclusive) of the range. The
incoming address must be less than this value.
64-bit Indicator (IS64L)—RO. Indicates that 32-bit addressing is supported for the limit. This
value must be in agreement with the IS64B field.
Prefetchable Memory Base (PMB)—R/W. These bits are compared with bits [31:20] of the
incoming address to determine the lower 1 MB aligned value (inclusive) of the range. The
incoming address must be greater than or equal to this value.
64-bit Indicator (IS64B)—RO. Indicates that 32-bit addressing is supported for the limit. This
value must be in agreement with the IS64L field.
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Intel^® 82870P2 P64H2 Datasheet