82870P2P64H2 Datasheet, PDF (85/217 Pages) –

Register Description
R
3.3.2.3
MCNF—Miscellaneous Configuration Register
Offset:
02–03h
Default Value: 00h
Attribute:
Size:
R/W, RO, R/WC
16 bits
This register contains various miscellaneous functions related to the hot plug controller.
Bits
Description
15 133 MHz Prescaler Indicator—RO. Hardwired to 0. This bit has no functionality in the P64H2.
Enable SERR on Power Fault (ESPF)—R/W.
0 = Disable. (default)
1 = Enable. When this bit is set, the assertion of a slot power fault pin causes SERR to be
asserted provided that:
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• SERR is enabled in the PCI configuration header Command Register, and
• The slot is fully powered on or is at least past the clock connect phase of a power-up
sequence.
Bit 10 (PFE) of this register must also be set to enable this function. Power faults can also
be programmed to generate interrupts independent of this bit, using the HMIR register.
Scan Power Fault Latches Enable (SPFLE)—R/W. The HMIC Register reflects the internal
latched version of the scan-in power fault bits (from the power fault latches) rather than the actual
13 _{scanned in power fault bits. Bit 10 (PFE) of this register must be set for this function to work.}
1 = Setting this bit to 1 when bit 10 (PFE) is 0 forces byte two of the HMIC to always read 1.
Input Scan Complete (ISC)—R/W.
12
0 = This bit is cleared at the conclusion of the next scan in sequence. (default)
1 = This bit can be written to 1 to ensure that fresh data is available when the input scan logic
reads input bytes [7:0].
66 MHz Enable (M66)—RO. When this bit is set, the hot plug controller clock source is 66 MHz.
11 0 = Disable (default)
1 = Enable. This bit is hardwired to 1 for P64H2.
Power Fault Enable (PFE)—R/W. This bit is mapped to bit 13 of the Miscellaneous
10 Configuration Register (PCI configuration space). Refer to the description of the PFE bit in the
MCNF Register in PCI configuration space for usage of this bit. (default=0)
Auto-Power Down Disable (APD)—R/W.
9
0 = Enable. (default)
1 = Disable. Disables powering down a slot when the slot switch is opened without first going
through software to power down the slot.
On/Off Busy (OOB)—RO. This bit is the same as bit 0 in the MCNF Register in PCI
configuration space (offset 42h).
0 = Not running (default)
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1 = Indicates the ON/OFF state machine is running. After RSTIN# is negated, this bit remains
set until the Intel® P64H2 updates the slot power, bus/clock enable, and reset controls for
the first time after software completes the initial write to the MCNF Register in PCI
configuration space.
Intel^® 82870P2 P64H2 Datasheet
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