82870P2P64H2 Datasheet, PDF (114/217 Pages) –

Functional Description
R
4.1.4
Data Bus
For supplying data, the P64H2 drives the following in the data phase:
• The low 32 bits of data on PxAD[31:0]
• The low four byte enable bits on PxC/BE[3:0]#
• The high 32 bits of data on PxAD[63:32] (64-bit data phases only)
• The high four byte enable bits on PxC/BE[7:4]# (64-bit data phases only)
As a PCI master, when the P64H2 drives PxREQ64# and detects PxACK64# asserted in the same
clock that it detects PxDEVSEL# asserted, every data phase then consists of 64 bits and eight byte
enable bits.
On write transactions, when the P64H2 does not detect PxACK64# asserted in the same clock that
it detects PxDEVSEL# asserted, it redirects all data to PxAD[31:0] and byte enables to
PxC/BE[3:0]#. For 64-bit memory-write transactions that end at an odd DWord boundary, the
P64H2 drives the byte enable bits to 1, and drive random but stable data on PxAD[63:32].
On read transactions, the P64H2 drives 8 bits of byte enables on PxC/BE[7:0]#. It generates byte
enables from hub interface byte enables, with the upper DWord driven on PxC/BE[7:4]#. If
PxACK64# is not sampled active with PxDEVSEL# active, then the P64H2 downshifts the all byte
enables PxC/BE[3:0]#.
The P64H2 does not assert PxREQ64# when initiating a transfer under the following conditions:
• The P64H2 is initiating an I/O transaction
• The P64H2 is initiating a configuration transaction
• The P64H2 is initiating a special cycle transaction
• A 1-DWord or 2-DWord transaction is being performed
• If the address of the hub interface initiated transaction is not QWord aligned
As a PCI target, the P64H2 does not assert PxACK64# when PxREQ64# was not asserted by the
initiator.
Posted
Posted write forwarding is used for memory write and for memory write-and-invalidate
transactions. When the P64H2 decodes a memory write transaction for the hub interface, it asserts
PxDEVSEL# and PxTRDY# in the same clock, provided that enough buffer space is available in
the posted data queue. The P64H2 adds no target wait states.
The P64H2 disconnects a write transaction when:
• The initiator terminates the transaction by deasserting PxFRAME# and PxIRDY#
• A 4 KB page boundary is reached
• The posted write data buffer fills up
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Intel^® 82870P2 P64H2 Datasheet