82870P2P64H2 Datasheet, PDF (168/217 Pages) –

Functional Description
R
4.7.1.3 Data Transfer Examples
For the following figures, the following terminology is used:
S Start Bit
Sr Start Repeat Bit
W Write Command
R Read Command
A Acknowledge
N Retry / not Acknowledge
P Stop Bit
The term “Clear” boxes indicate phases of the cycle driven by the initiator, and shaded boxes
indicate phases of the cycle driven by the P64H2.
In Figure 12 an initiator targets the P64H2 with a write, which retries the cycle. Since all read
cycles will first be set up with a write to the register index stack pointer, the P64H2 will only be
busy on a write cycle. For example, if a command had been written indicating a DWord read from
a bus/device-function/register number, the P64H2 will be busy doing the read when the subsequent
write comes into the Register Index.
Figure 12. Intel^® P64H2 Busy
S
Slave Address
WN P
smbus_busy
In Figure 13 an initiator targets the P64H2 with a write to a P64H2 register. The P64H2 accepts
the cycle, and the master sends the Command Register, Bus Number Register, Device/Function
Number Register, Register Number Register, and data bytes in subsequent bytes. In this example,
the master is sending two bytes (to data 0 and data 1) because the command register was a “word
write”.
The master could have written more or fewer bytes – in the case of a word write, it is not
guaranteed that the master will send both bytes or even all the address information.
Figure 13. Intel^® P64H2 Busy
S
Slave Address
W A 0000_0000 (Register Index) A
Command
A
Bus Number
A
Device/Function Num ber
A
Register Number
A
Data Byte 0
A
Data Byte 1
AP
smbus_busy_1
168
Intel^® 82870P2 P64H2 Datasheet