82870P2P64H2 Datasheet, PDF (110/217 Pages) –

Register Description
R
3.5.3.1
3.5.4
DATA—Data Register
Offset:
04–07h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
This register is used to read or write data to the desired configuration register. At the completion
of a Read command, this register contains the data from the selected configuration register. For
reads, the data register will always return 32 bits and will always be aligned on a DWord
boundary.
Before issuing a write command this register should be written with the desired write data. For a
byte write, only the D[7:0] data will be written to the desired configuration register. For a word
write, only the D[15:0] data will be written to the desired configuration register. The register
number must be word aligned for word writes. For a DWord write, all 32 bits of data will be used.
The register number must be DWord aligned.
The Status Register should be checked to make sure that there is not a command currently in
progress, before writing to this register. Writing to this register when the Busy bit in the Status
Register is asserted will have indeterminate effects.
Bits
31:24
23:16
15:8
7:0
Byte 3 (B3). Data bits [31:24]
Byte 2 (B2). Data bits [23:16]
Byte 1 (B1). Data bits [15:8]
Byte 0 (B0). Data bits [7:0]
Description
CFG—SMBus Configuration Register
Offset:
FFh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This register contains various configuration options for the SMBus controller. When this register
is accessed, an internal configuration cycle on SMBus is not launched.
Bits
Description
7:1 Reserved
ICH Block Mode.
0
1 = Indicates that the Intel® P64H2 SMBus controller should accept commands as if they were
ICH block mode commands.
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Intel^® 82870P2 P64H2 Datasheet