82870P2P64H2 Datasheet, PDF (193/217 Pages) –

Electrical Characteristics
R
5.2.2 PCI-X Interface Timing
Table 80. PCI-X General Timing Parameters (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%,
Tcase=0qC to 105qC)
PCI-X 133
PCI-X 66
Sym
Parameter
Min
Max
Min
Max Units Notes
Tval
PxPCLKO[6:0] to Signal Valid
Delay-bused signals
0.7
3.8
0.7
3.8
ns 1, 2, 3,
10, 11
Tval(ptp) PxPCLKO[6:0] to Signal Valid
Delay-point to point signals
0.7
3.8
0.7
3.8
ns 1, 2, 3,
10, 11
Ton
Float to Active Delay
0
0
ns 1, 7, 10,
11
Toff
Active to Float Delay
7
7
ns 1, 7, 11
Tsu
Input Setup Time to
1.2
1.7
ns 3, 4, 8
PxPCLKO[6:0]-Bused signals
Tsu(ptp) Input Setup Time to
1.2
1.7
ns 3, 4
PxPCLKO[6:0]-point to point
Th
Input Hold Time from
PxPCLKO[6:0]
0.5
0.5
ns 4
Trst
Reset Active Time after power
1
stable
1
ms 5
Trst-clk
Reset Active Time after
100
100
PxPCLKO[6:0] stable
µs 5
Trst-off
Reset Active to output float delay
40
40
ns 5, 6
Trrsu
PxREQ64# to RSTIN# setup
10
10
ns
time
Trrh
RSTIN# to PxREQ64# hold Time
0
50
0
50
ns
Trhfa
RSTIN# high to first configuration
2²⁷
access
2²⁷
clocks
Trhff
RSTIN# high to first PxFRAME#
5
Assertion
5
clocks
Tpvrh
Power valid to RSTIN# high
100
100
ms
Tprsu
PCI-X initialization pattern to
10
RSTIN# setup time
10
clocks
Tprh
RSTIN# to PCI-X initialization
pattern hold time
0
50
0
50
ns 9
Trlcx
Delay from RSTIN# low to
0
PxPCLKO[6:0] frequency change
0
ns
NOTES:
1. Refer to Figure 20. For timing and measurement condition details, refer to the PCI-X Addendum to the
PCI Local Bus Specification document.
2. Minimum times are measured at the package pin (not the test point).
Intel^® 82870P2 P64H2 Datasheet
193