82870P2P64H2 Datasheet, PDF (145/217 Pages) –

Functional Description
R
Power Up (CBL Mode)
When a slot is to be turned on in CBL mode (power-up default), the outputs are updated in the
following sequence:
1. Assert PWREN, but keep BUSEN# and CLKEN# deasserted and RESET# asserted. Shift the
new pattern to the shift registers.
2. Clock the parallel latch HP_SOL. The new values for LEDs are clocked out at this point as
well.
3. With PWREN asserted, assert CLKEN# bit but leave BUSEN# deasserted and RESET#
asserted. Shift the new pattern to the shift registers.
4. Wait for 500 ms for power to stabilize.
5. Arbitrate for an idle bus, and clock the parallel latch HP_SOL.
6. With PWREN and CLKEN# asserted, assert BUSEN# to connect the bus, and deassert
RESET# Shift the new pattern to the shift registers.
7. Wait for 500 ms for expansion card clocks to stabilize.
8. Clock the parallel latch HP_SOLR, to negate reset. However, since HP_SOL is not clocked,
the BUSEN# pin remains deasserted to the device.
9. Wait for 500 ms.
10. Arbitrate for an idle bus time, and clock the parallel latch HP_SOL.
Table 42. Power Up Timings (CBL Mode)
Timing Event
PWREN Assertion to CLKEN# Assertion
CLKEN# Assertion to RESET# Deassertion
RESET# De-assertion to BUSEN# Assertion
NOTES:
1. Arbitration latency affects the minimum time.
Minimum¹
500
500
500
Maximum
505
505
505
Units
ms
ms
ms
Power Down (CBL Mode)
When a slot is to be turned off in CBL mode (power-up default), the outputs are updated in the
following sequence:
1. Assert RESET# and negate the BUSEN# but leave CLKEN# asserted and PWREN asserted.
Shift the new pattern to the shift registers.
2. Arbitrate for an idle bus and clock the parallel latch HP_SOL, which asserts BUSEN# to the
card. Since HP_SOLR is not clocked, RESET# stays asserted.
3. Wait 330 ns and clock the parallel latch HP_SOLR to assert RESET#.
4. With RESET# asserted and BUSEN# deasserted, deassert CLKEN# but leave PWREN
asserted. Shift the new pattern to the shift registers.
5. Arbitrate for an idle bus and clock the parallel latch HP_SOL.
6. With RESET# asserted and BUSEN# and CLKEN# deasserted, deassert PWREN. Shift the
new pattern to the shift registers.
7. Clock the parallel latch HP_SOL.
Intel^® 82870P2 P64H2 Datasheet
145