82870P2P64H2 Datasheet, PDF (77/217 Pages) –

Register Description
R
Bits
Description
Inhibit Bus Connect (IBC)—R/W. This bit controls the method in which cards will be powered up
following a cold boot.
0 = Hot plug slots will be fully enabled (Default). That is, the slots will be powered on, connected
to the bus and brought out of reset when the system software writes to configuration offset
43h.
4
1 = Hot plug slots will only be powered on when system software writes to configuration offset
43h. This feature can be used to more efficiently determine the state of the slot input pins
such as M66EN or PCIXCAP pins. Otherwise, the bus must be set to 33 MHz and a lengthy
power up sequence must be executed before the state of the slots can be inspected. After
the power enable only (no bus connect) power-up sequence, system software clears this bit
and writes to 43h again to fully enable the slots. The OOB bit is monitored to determine
when power sequences are complete.
Enable Master Abort Detection SERR (EMAS)—R/W.
3
0 = Disable (Default).
1 = SERR is generated when a PCI memory or I/O cycle is aborted by the PCI initiator.
2
Reserved
Enable CBL Power Sequencing Mode (CBLE)—R/W. When operating in one slot mode with no
isolation switches, software must not set this bit to 1 and must always use CBF mode.
1
0 = Disable. The power sequence state machine will connect the bus first. In CBF mode, bus
connect occurs before reset deassertion when powering up a slot.
1 = Enable. (Default)
On / Off Busy Status (OOB)—RO.
1 = Indicates the ON/OFF state machine is running. After RSTIN# is negated, this bit remains
0
set until the P64H2 updates the slot power, bus/clock enable, and reset controls for the first
time after software completes the initial write to configuration register offset 43h. (Default)
Note: This bit is the same as bit 8 in MCNF Register in memory space (offset 02h).
Intel^® 82870P2 P64H2 Datasheet
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