82870P2P64H2 Datasheet, PDF (23/217 Pages) –

Signal Description
R
Table 3. PCI Bus Interface B Signals
Signal
PBAD[31:0]
PBC/BE[3:0]#
PBPAR
PBDEVSEL#
PBFRAME#
PBIRDY#
PBTRDY#
PBSTOP#
PBPERR#
PBSERR#
PBREQ[5:0]#
PBGNT[5:0]#
Type
Description
PCI Address/Data: These signals are a multiplexed address and data bus.
I/O
During the address phase or phases of a transaction, the initiator drives a
physical address on PBAD[31:0]. During the data phases of a transaction, the
initiator drives write data, or the target drives read data.
Bus Command and Byte Enables: These signals are a multiplexed command
field and byte enable field. During the address phase or phases of a
I/O transaction, the initiator drives the transaction type on PBC/BE[3:0]#. For both
read and write transactions, the initiator drives byte enables on PBC/BE[3:0]#
during the data phases.
Parity: Even parity calculated on 36 bits (AD[31:0] plus PBC/BE[3:0]#). It is
I/O
calculated on all 36 bits, regardless of the valid byte enables. It is driven
identically to the PBAD[31:0] lines, except it is delayed by exactly one PCI
clock.
Device Select: The Intel® P64H2 asserts PBDEVSEL# to claim a PCI
transaction. As a target, the P64H2 asserts PBDEVSEL# when a PCI master
peripheral attempts an access to an internal address or an address destined
I/O for the hub interface. As an initiator, PBDEVSEL# indicates the response to a
P64H2-initiated transaction on the PCI bus. PBDEVSEL# is tri-stated from the
leading edge of PCIRST#. PBDEVSEL# remains tri-stated by the P64H2 until
driven as a target.
Frame: PBFRAME# is driven by the Initiator to indicate the beginning and
I/O duration of an access. While PBFRAME# is asserted, data transfers continue.
When PBFRAME# is negated, the transaction is in the final data phase.
Initiator Ready: PBIRDY# indicates the ability of the initiator to complete the
I/O current data phase of the transaction. A data phase is completed when both
PBIRDY# and PBTRDY# are sampled asserted.
Target Ready: PBTRDY# indicates the ability of the target to complete the
current data phase of the transaction. A data phase is completed when both
I/O PBTRDY# and PBIRDY# are sampled asserted. PBTRDY# is tri-stated from
the leading edge of PCIRST#. PBTRDY# remains tri-stated by the P64H2 until
driven as a target.
I/O
Stop: PBSTOP# indicates that the target is requesting an initiator to stop the
current transaction.
Parity Error: PBPERR# is driven by an external PCI device when it receives
I/O
data that has a parity error. It is driven by the P64H2 when, as an initiator it
detects a parity error during a read transaction and as a target during write
transactions.
System Error: PBSERR# can be pulsed active by any PCI device that detects
I a system error condition except the P64H2. The P64H2 samples PBSERR# as
an input and conditionally forwards it to the hub interface.
PCI Requests: PBREQ[5:0]# supports up to six masters on the PCI bus. The
I P64H2 accepts six request inputs into its internal bus arbiter. The P64H2
request input to the arbiter is an internal signal.
PCI Grants: PBGNT[5:0]# supports up to six masters on the PCI bus. The
arbiter can assert one of the six bus grant outputs to indicate that an initiator
O _{can start a transaction on the PCI bus.}
Intel^® 82870P2 P64H2 Datasheet
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