82870P2P64H2 Datasheet, PDF (176/217 Pages) –

Functional Description
R
4.9.1
4.9.2
Error Types
P64H2 errors are classified into two categories, those that are considered fatal and those that are
considered non-fatal.
The non-fatal class of errors are:
• Cycles that are Target or Master Aborted on the hub interface and PCI.
• Single bit ECC errors (command or data) on the hub interface.
The fatal class of errors are:
• Data and Command errors on outbound cycles from the hub interface.
• Data and Command errors on inbound cycles from PCI.
• Data errors that are a result of failures on the internal SRAM for outbound cycles.
• Data errors that are a result of failures on the internal SRAM for inbound cycles.
When an error is logged, the RASERR# pin will be driven active. This pin will remain active until
software clears the status bit that caused the error. This pin is a level mode pin. It is simply an OR
of the status bits shown in bits [13:8] and bits [5:0] of the RAS_STS Register (offset 60h).
Non-fatal errors can be optionally disabled, by clearing the ENFE bit in the RAS_STS Register
(bit 15 of offset 60h). If this bit is cleared, non-fatal errors do not set the RASERR# pin, although
the errors are still logged and the status bit set. This disable allows less intelligent system
management controllers, which may simply reboot the system on an error, from rebooting the
system due to a master abort or single bit ECC error.
Error Logging
When the first error is caught on an interface, subsequent errors for the error class for that bridge
are not recorded. However, errors on the other bridge can still be recorded. Additionally, if a non-
fatal error occurs on the bridge, then is followed later by a fatal error on that same bridge, the fatal
error overrides the non-fatal error, and the fatal error is logged. However, a non-fatal error cannot
override a previous non-fatal error.
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Intel^® 82870P2 P64H2 Datasheet