82870P2P64H2 Datasheet, PDF (44/217 Pages) –

Register Description
R
3.2.12
IOBL_ADR—I/O Base and Limit Address Register
D29,31: F04
Offset:
1C–1Dh
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
This register defines the base and limit (aligned to a 4 KB boundary) of the I/O area of the bridge.
Accesses from the hub interface that are within the ranges specified in this register will be sent to
PCI if the I/O space enable bit is set. Accesses from PCI that are outside the ranges specified will
master abort.
Bits
15:12
11:10
9:8
7:4
3:2
1:0
Description
I/O Limit Address Bits [15:12] (IOLA)—R/W. Defines the top address of an address range to
determine when to forward I/O transactions from one interface to the other. These bits
correspond to address lines 15:12 for 4 KB alignment. Bits [11:0] are assumed to be FFFh.
I/O Limit Address Bits [11:10] (IOLA1K)—R/W, RO. When the EN1K bit is set in the Intel®
P64H2 Configuration register (CNF), these bits become read/write and are compared with I/O
address bits [11:10] to determine the 1 KB limit address.
When the EN1K bit is cleared, this field becomes read only.
I/O Limit Addressing Capability (IOLC)—RO. Hardwired to 00. This indicates support for only
16-bit I/O addressing.
I/O Base Address Bits [15:12] (IOBA)—R/W. This filed defines the bottom address of an
address range to determine when to forward I/O transactions from one interface to the other.
These bits correspond to address lines 15:12 for 4 KB alignment. Bits [11:0] are assumed to be
000h.
I/O Base Address Bits [11:10] (IOBA1K)—R/W, RO. When the EN1K bit is set in the P64H2
Configuration register (CNF), these bits become read/write and are compared with I/O address
bits [11:10] to determine the 1 KB base address. When the EN1K bit is 0, this field becomes read
only.
I/O Base Addressing Capability (IOBC)—RO. Hardwired to 00. This indicates support for only
16-bit I/O addressing.
3.2.13
SECSTS—Secondary Status Register (D29,31: F0)
Offset:
1E–1Fh
Default Value: 02A0h
Attribute:
Size:
R/WC, RO
16 bits
Bits
Description
Detected Parity Error (DPE)—R/WC.
0 = No address or data parity error detected.
15
1 = Intel® P64H2 detects an address or data parity error on the PCI bus. This bit gets set even
if the Parity Error Response bit (bit 0 of offset 3E–3Fh) is not set.
Note: Software clears this bit by writing a 1 to it.
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Intel^® 82870P2 P64H2 Datasheet