82870P2P64H2 Datasheet, PDF (97/217 Pages) –

Register Description
R
3.4.1.4
3.4.1.5
PCISTS—PCI Device Status Register (D28,30: F0)
Offset:
06–07h
Default Value: 0030h
Attribute:
Size:
R/W, RO, R/WC
16 bits
None of the bits in the I/OxAPIC status register are read/write.
Bits
Description
Detected Parity Error (DPE)—R/WC.
0 = No parity error detected. (default)
15
1 = Indicates that a parity error was detected on cycles targeting the I/OxAPIC.
Note: Software clears this bit by writing a 1 to it.
Signaled System Error (SSE)—R/WC.
0 = No SERR# reported. (default)
14
1 = SERR# is reported to the hub interface via the DO_SERR special cycle.
Note: Software clears this bit by writing a 1 to it.
13 Received Master Abort (RMA)—RO. Hardwired to 0; Reserved
12 Received Target Abort (RTA)—RO. Hardwired to 0; Reserved.
11 Signaled Target Abort (STA)—RO. Hardwired to 0; Reserved.
10:9 DEVSEL# Timing (DT)—RO. Fast decode is performed by the I/OxAPIC.
8
Master Data Parity Error (MDPE)—RO. Hardwired to 0; Reserved.
7
Fast Back-to-Back Capable (FBC)—RO. Hardwired to 0; Reserved as not fast back-to-back
capable.
6
Reserved
5
66 MHz Capable (C66)—RO. Hardwired to 1; 66 MHz capable.
Capabilities List Enable (CAPE)—RO. Hardwired to 1; This bit indicates that the Intel® P64H2
4
contains the capabilities pointer in the I/OxAPIC. Offset 34h indicates the offset for the first entry
in the linked list of capabilities.
3:0 Reserved
RID—Revision ID Register (D28,30: F0)
Offset:
08h
Default Value: 04h
Attribute:
Size:
RO
8 bits
Bits
Description
Revision ID (RID). Indicates the step of the I/OxAPIC in the Intel® P64H2.
7:0 _{03h = B0 Stepping}
04h = B1 Stepping
Intel^® 82870P2 P64H2 Datasheet
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