82870P2P64H2 Datasheet, PDF (41/217 Pages) –

Register Description
R
3.2.5
3.2.6
Bits
Description
6
Reserved
5
66 MHz Capable (C66)—RO. Hardwired to 1. This bit has no meaning on the hub interface, but
is set to be true in case of any software dependencies on bandwidth calculations.
Capabilities List Enable (CAPE)—RO. This bit indicates that the P64H2 contains the
4
capabilities pointer in the bridge. The register at offset 34h (Capabilities List Pointer) indicates
the offset for the first entry in the linked list of capabilities.
3:0 Reserved
RID—Revision ID Register (D29,31: F0)
Offset:
08h
Default Value: 04h
Attribute:
Size:
RO
8 bits
Bits
Description
Revision ID (RID). This field indicates the stepping of the Intel® P64H2:
7:0 _{03h = B0 Stepping}
04h = B1 stepping
CC—Class Code Register (D29,31: F0)
Offset:
09–0Bh
Default Value: 060400h
Attribute:
Size:
RO
24 bits
This contains the class code, sub class code, and programming interface for the device.
Bits
Description
23:16
15:8
7:0
Base Class Code (BCC).
06h = Bridge device.
Sub Class Code (SCC).
04h = Type of PCI-PCI bridge.
Programming Interface (PIF).
00h = Standard (non-subtractive) PCI-PCI bridge.
Intel^® 82870P2 P64H2 Datasheet
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